Particular problems arise with making connections to a host of various different materials and/or surfaces. Adhesives, welding, brazing, soldering, and other forms of bonding, such as thermoplastic bonding, molecular bonding and so on are but a few of the most common techniques available to the man skilled in the art. These examples are not intended to be limiting in any way. Bond strength is a major consideration in the selection of the type of bond and the method of implementing it. The ultimate bond strength can be determined by a variety of factors, such as the nature and properties of the materials to be bonded, the nature and properties of the bonding materials or media, the conditions under which the bonding process is carried out and the conditions of use of the article or device employing the bond once made. Likewise, these examples are not intended to be limiting but are mentioned merely as an aid to understanding the advances made by the present invention.
Although there are general problems, such as those outlined above, which may be encountered in a host of different technologies, there are specific problems that have to be faced in certain, well-defined technologies. One such technology relates to the provision of connections to/from electronic circuitry. These connections are primarily electrical but can also perform the function of a mechanical connection. The converse can also be true. For example, there are currently several known methods for forming electrical/mechanical connections between two carriers such as, for example, an integrated circuit (IC) and a ceramic interposer.
One common method of forming such connections involves bonding suitable conductive wires between bond pads formed on the IC, and respective pads carried by the associated carrier. The wires are bonded using well known thermosonic techniques that utilise ultrasonic and thermal energy to form the required bonds.
A second known method of such connection is known in the art as “bumped die” or “flip chip” bonding. This second method involves the formation of contacts, typically in the form of balls, studs or hemispherical bumps, on the bond pads of the IC. The IC can then be connected to the carrier by bonding the contacts of the IC to appropriate corresponding bonding surfaces of the carrier. The bonding can be carried out using known: thermal compression; thermosonic; soldering; and/or adhesive bonding techniques, including combinations thereof.
A third known method of such connection is known in the art as “tape automated bonding” or “TAB bonding”. TAB bonding involves the bonding of a carrier's conductive trace directly onto the bond pads of the IC.
Each of the above three connection methods exhibits disadvantages, especially, for example, when applied to components having high pin counts and/or where there is a need for chip size/scale packages (CSP's). For example, thermosonic wire bonding and TAB bonding methods have a disadvantage in that the bond pads must be placed about the periphery of the IC. Another disadvantage of these methods is that the connections from the IC to the carrier are relatively long, and as such, present many well known and understood problems associated with the routing of signals, especially high frequency signals, due to unwanted parasitic elements. Furthermore, another disadvantage associated with thermosonic wire bonding and TAB bonding techniques is that, as the physical size of an IC gets smaller, the IC becomes bond pad limited. Bond pad limitation occurs when the size of the IC is determined by the number of connections that need to be made between the IC and the carrier, and not by the functionality of the IC. This is still the case even when multiple rows of the finest available pitch (typically less than 100 microns) of bond pads are used. For a given yield of die per wafer, the physical size of the IC directly affects the absolute number of “known good die” (KGD) per wafer, and so being limited to a minimum size by bond pad considerations has serious cost implications and such a situation is therefore undesirable and disadvantageous.
One disadvantage associated with flip chip technology is that it does not permit the use of the same fine pitch bond pads that are currently available for thermosonic wire bonding or TAB bonding connection techniques. Typical pitch values for current flip chip technology are greater than 200 microns. However, flip chip technology does have an advantage over thermosonic wire bonding and TAB bonding techniques in that the positioning of the bond pads is not limited. Using flip chip technology, operative bond pads can be placed, for example, in an area array all over the top surface of an IC. A disadvantage associated with flip chip technology is that the balls, studs or hemispherical bumps, that are employed are limited in height because of the fine pitch requirements i.e. the aspect ratio (AR) of a contact's height (h) to its diameter (d3) is typically less than one (AR h:d3 1) and quite often less than 0.7. The problem of having contacts with such low value aspect ratios is that the resulting connections of the IC to the carrier, for example, tend to transmit mechanical stresses, caused by the different coefficients of thermal expansion (CTE) of the IC and carrier materials, between the IC and its associated carrier. One solution to the problem associated with the different CTE's of IC and carrier materials is to ensure that the difference between the CTE of the IC and the carrier are within acceptable limits for the size of the IC and its operating temperature range. However, matching such IC and carrier CTE's has an associated disadvantage in that the matching can involve the use of expensive specialist carrier materials. It should be noted that as the semiconductor industry moves towards greater system integration, i.e. system-on-chip and multi-chip-modules, the inherently larger IC's compound the present problems of CTE matching. These larger IC's result in greater mechanical stresses, which results in more attention having to be paid to solving the matching problems associated with the different coefficients of thermal expansion (CTE) of the IC and its associated carrier.
In addition to the problems associated with bump-like connections of an electrical/electronic nature, as discussed above, there are also limitations as regards mechanical integrity and mechanical shock. These problems can also occur in a non-electrical/electronic applications. Prior art connections, whether they are of a mechanical or electrical/electronic nature, are of limited extension (height) relative to the plane on which they are made. Typical aspect ratio figures of less than unity have already been mentioned. One consequence not necessarily related to differential thermal expansion is the inherent rigidity in the transverse direction, i.e. parallel to the plane of the surface and/or device on which the connection is provided. Increasing the height would have the advantageous effect that the lateral stiffness would be reduced, thereby increasing the resistance of the device to lateral forces that might otherwise disturb or damage the connection between the surface and a device or other surface.
In light of the foregoing problems associated with the state of the art, it is desirable to provide an improved method of forming connections, such as electrical/mechanical connections, between a surface and another element, such as a connection between a plurality of electronic carriers. It is also desirable to provide an improved method of forming high stress tolerant electrical/mechanical connections that are suitable for use with a variety of electronic carriers.